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| 1 (R) XC95144 In-System Programmable CPLD 1 1* December 4, 1998 (Version 4.0) Product Specification Operating current for each design can be approximated for specific operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC95144 device. Features * * * * * 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz 144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3 V or 5 V I/O capability Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 100-pin PQFP, 100-pin TQFP, and 160-pin PQFP packages * * * * * * * * * * * * 600 (480) Typical ICC (mA) 400 High Perf nce orma (320) (300) 200 (160) er Pow Low 0 Description The XC95144 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 3,200 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview. 50 Clock Frequency (MHz) 100 X5898B Figure 1: Typical Icc vs. Frequency for XC95144 Power Management Power dissipation can be reduced in the XC95144 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. December 4, 1998 (Version 4.0) 1 XC95144 In-System Programmable CPLD 3 JTAG Port 1 JTAG Controller In-System Programming Controller 36 I/O I/O I/O I/O FastCONNECT Switch Matrix 36 18 18 Function Block 1 Macrocells 1 to 18 Function Block 2 Macrocells 1 to 18 I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2 36 18 Function Block 3 Macrocells 1 to 18 36 18 Function Block 4 Macrocells 1 to 18 36 18 Function Block 8 Macrocells 1 to 18 X5922 Figure 2: XC95144 Architecture Function Block outputs (indicated by the bold line) drive the I/O Blocks directly. 2 December 4, 1998 (Version 4.0) XC95144 In-System Programmable CPLD Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL Parameter Supply voltage relative to GND DC input voltage relative to GND Voltage applied to 3-state output with respect to GND Storage temperature Max soldering temperature (10 s @ 1/16 in = 1.5 mm) Value -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -65 to +150 +260 Units V V V C C Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Recommended Operation Conditions Symbol VCCINT VCCIO VIL VIH VO Parameter 1 Min 4.75 (4.5) 4.75 (4.5) 3.0 0 2.0 0 Max 5.25 (5.5) 5.25 (5.5) 3.6 0.80 VCCINT +0.5 VCCIO Units V V V V V V Supply voltage for internal logic and input buffer Supply voltage for output drivers for 5 V operation Supply voltage for output drivers for 3.3 V operation Low-level input voltage High-level input voltage Output voltage Note: 1. Numbers in parenthesis are for industrial-temperature range versions. Endurance Characteristics Symbol tDR NPE Data Retention Program/Erase Cycles Parameter Min 20 10,000 Max Units Years Cycles December 4, 1998 (Version 4.0) 3 XC95144 In-System Programmable CPLD DC Characteristics Over Recommended Operating Conditions Symbol VOH Parameter Output high voltage for 5 V operation Output high voltage for 3.3 V operation VOL Output low voltage for 5 V operation Output low voltage for 3.3 V operation IIL IIH CIN ICC Input leakage current I/O high-Z leakage current I/O capacitance Operating Supply Current (low power mode, active) Test Conditions IOH = -4.0 mA VCC = Min IOH = -3.2 mA VCC = Min IOL = 24 mA VCC = Min IOL = 10 mA VCC = Min VCC = Max VIN = GND or VCC VCC = Max VIN = GND or VCC VIN = GND f = 1.0 MHz VI = GND, No load f = 1.0 MHz Min 2.4 2.4 0.5 0.4 10.0 10.0 10.0 160 (Typ) Max Units V V V V A A pF ma AC Characteristics Symbol tPD tSU tH tCO fCNT1 fSYSTEM 2 tPSU tPH tPCO tOE tOD tPOE tPOD tWLH Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter frequency Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock to output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GCK pulse width (High or Low) XC95144-7 Min 4.5 0.0 4.5 125.0 83.3 0.5 4.0 8.5 5.5 5.5 9.5 9.5 4.0 4.5 111.1 66.7 2.0 4.0 10.0 6.0 6.0 10.0 10.0 5.5 Max 7.5 6.0 0.0 6.0 95.2 55.6 4.0 4.0 12.0 11.0 11.0 14.0 14.0 XC95144-10 XC95144-15 Min Max 10.0 8.0 0.0 8.0 Min Max 15.0 Units ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns Note: 1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable. fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG. 2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs. 4 December 4, 1998 (Version 4.0) XC95144 In-System Programmable CPLD VTEST R1 Device Output R2 CL Output Type VCCIO 5.0 V 3.3 V VTEST 5.0 V 3.3 V R1 160 260 R2 120 360 CL 35 pF 35 pF X5906 Figure 3: AC Load Circuit Internal Timing Parameters Symbol Parameter XC95144-7 Min Max 2.5 1.5 4.5 5.5 2.5 0.0 3.0 2.0 4.5 0.5 1.5 3.0 0.5 6.5 7.5 2.0 10.0 8.0 4.0 1.0 4.0 10.0 2.5 11.0 9.5 3.5 1.0 4.5 2.5 3.5 0.5 7.0 10.0 3.0 11.5 11.0 3.5 1.0 5.0 XC95144-10 XC95144-15 Min Max 3.5 2.5 6.0 6.0 3.0 0.0 3.0 2.5 3.5 1.0 3.5 4.5 0.5 8.0 Min Max 4.5 3.0 7.5 11.0 4.5 0.0 2.5 3.0 5.0 3.0 Units Buffer Delays tIN Input buffer delay tGCK GCK buffer delay tGSR GSR buffer delay tGTS GTS buffer delay tOUT Output buffer delay tEN Output buffer enable/disable delay Product Term Control Delays tPTCK Product term clock delay tPTSR Product term set/reset delay tPTTS Product term 3-state delay Internal Register and Combinatorial delays tPDI Combinatorial logic propagation delay tSUI Register setup time tHI Register hold time tCOI Register clock to output valid time tAOI Register async. S/R to output delay tRAI Register async. S/R recovery before clock tLOGI Internal logic delay tLOGILP Internal low power logic delay Feedback Delays tF FastCONNECT matrix feedback delay tLF Function Block local feedback delay Time Adders tPTA3 Incremental Product Term Allocator delay tSLEW Slew-rate limited delay ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: 3. tPTA is multiplied by the span of the function as defined in the family data sheet. December 4, 1998 (Version 4.0) 5 XC95144 In-System Programmable CPLD XC95144 I/O Pins Function Macrocell Block 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 TQ 100 - 11 12 - 13 14 - 15 16 - 17 18 - 19 20 - 22 - - 99 - - 1 2 - 3 4 - 6 7 - 8 9 - 10 - PQ 100 - 13 14 - 15 16 - 17 18 - 19 20 - 21 22 - 24 - - 1 - - 3 4 - 5 6 - 8 9 - 10 11 - 12 - PQ BScan Notes 160 Order 25 18 19 27 21 22 32 23 24 34 26 28 38 29 30 39 33 - 158 159 3 5 2 4 7 6 8 9 11 12 14 13 15 16 17 - 429 426 423 420 417 414 411 408 405 402 399 396 393 390 387 384 381 378 375 372 369 366 363 360 357 354 351 348 345 342 339 336 333 330 327 324 Function Macrocell Block 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 TQ 100 - 23 - - 24 25 - 27 28 - 29 30 - 32 33 - 34 - - 87 - - 89 90 - 91 92 - 93 94 - 95 96 - 97 - PQ 100 - 25 - - 26 27 - 29 30 - 31 32 - 34 35 - 36 - - 89 - - 91 92 - 93 94 - 95 96 - 97 98 - 99 - PQ 160 43 35 45 48 36 37 50 42 44 52 47 49 53 54 56 55 57 - 132 140 147 149 142 143 150 144 145 151 146 148 153 152 154 155 156 - BScan Notes Order 321 318 315 312 309 306 303 300 297 294 291 288 285 282 279 276 273 270 267 264 261 258 255 252 249 246 243 240 237 234 231 228 225 222 219 216 [1] [1] [1] [1] [1] [1] [1] [1] Notes: [1] Global control pin. Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG and Global Signals are fixed. 6 December 4, 1998 (Version 4.0) XC95144 In-System Programmable CPLD XC95144 I/O Pins (continued) Function TQ Macrocell Block 100 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 35 - - 36 37 - 39 40 - 41 42 - 43 46 - 49 - - 74 - - 76 77 - 78 79 - 80 81 - 82 85 - 86 - PQ 100 - 37 - - 38 39 - 41 42 - 43 44 - 45 48 - 51 - - 76 - - 78 79 - 80 81 - 82 83 - 84 87 - 88 - PQ 160 65 58 66 67 59 60 74 62 63 76 64 68 78 69 72 83 77 - - 117 119 123 122 124 125 126 129 128 133 134 130 135 138 131 139 - BScan Notes Order 213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108 Function Macrocell Block 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 TQ 100 - 50 - - 52 53 - 54 55 - 56 58 - 59 60 - 61 - - 63 - - 64 65 - 66 67 - 68 70 - 71 72 - 73 - PQ 100 - 52 - - 54 55 - 56 57 - 58 60 - 61 62 - 63 - - 65 - - 66 67 - 68 69 - 70 72 - 73 74 - 75 - PQ 160 - 79 84 85 82 86 87 88 90 89 92 95 91 96 97 93 98 - - 101 105 107 102 103 109 104 106 112 108 111 114 113 115 118 116 - BScan Notes Order 105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0 December 4, 1998 (Version 4.0) 7 XC95144 In-System Programmable CPLD XC95144 Global, JTAG and Power Pins Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TCK TDI TDO TMS VCCINT 5 V VCCIO 3.3 V/5 V GND TQ100 22 23 27 3 4 1 2 99 48 45 83 47 5, 57, 98 26, 38, 51, 88 100, 21, 31, 44, 62, 69, 75, 84 - PQ100 24 25 29 5 6 3 4 1 50 47 85 49 7, 59, 100 28, 40, 53, 90 2, 23, 33, 46, 64, 71, 77, 86 - PQ160 33 35 42 6 8 2 4 159 75 71 136 73 10, 46, 94, 157 1, 41, 61, 81, 121, 141 20, 31, 40, 51, 70, 80, 99, 100, 110, 120, 127, 137, 160 - No Connects 8 December 4, 1998 (Version 4.0) XC95144 In-System Programmable CPLD Ordering Information XC95144 -7 PQ 160 C Device Type Temperature Range Number of Pins Speed Package Type Speed Options -15 15 ns pin-to-pin delay -10 10 ns pin-to-pin delay -7 7 ns pin-to-pin delay Packaging Options PQ100 100-Pin Plastic Quad Flat Pack (PQFP) TQ100 100-Pin Very Thin Quad Flat Pack (TQFP) PQ160 160-Pin Plastic Quad Flat Pack (PQFP) Temperature Options C I Commercial Industrial 0C to 70C -40C to 85C Component Availability Pins Type Code XC95144 -15 -10 -7 100 Plastic PQFP PQ100 C,I C,I C Plastic TQFP TQ100 C,I C,I C 160 Plastic PQFP PQ160 C,I C,I C C = Commercial = 0C to +70C I = Industrial = -40C to +85C Revision Control Date 12/04/98 Revision Update AC characteristics and internal parameters. December 4, 1998 (Version 4.0) 9 |
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